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//! CPU specific funcitions

use core::arch::asm;
use core::mem::size_of;
use core::sync::atomic::{AtomicU32, Ordering};

use super::int::apic::LAPIC_IDS;
use super::int::lapic::LAPIC;
use crate::MAX_CPUS;

static ONLINE_MASK: AtomicU32 = AtomicU32::new(0);
const _: () = assert!(MAX_CPUS <= size_of::<AtomicU32>() * 8);

/// Halt the cpu
pub fn halt() {
    unsafe { asm!("hlt", options(nomem, nostack)) };
}

/// Initialize the CPU
pub fn init(core: usize) {
    ONLINE_MASK.fetch_or(1 << core, Ordering::AcqRel);
}

/// Returns the CPU ID
pub fn id() -> usize {
    // The lapic defines the (hierarchical) CPU ID.
    // We assume these IDs are contiguous, which is not guaranteed on multi-NUMA systems.
    if let Some(ids) = LAPIC_IDS.get() {
        let lapic_id = LAPIC.id();
        ids.iter()
            .position(|v| *v == lapic_id)
            .unwrap_or(0)
    } else {
        0
    }
}

/// Returns a bitmap of online CPUs
pub fn online() -> u32 {
    ONLINE_MASK.load(Ordering::Acquire)
}

/// Return an iterator over all online CPUs
pub fn iter() -> impl Iterator<Item = usize> {
    let mask = ONLINE_MASK.load(Ordering::Acquire);
    (0..MAX_CPUS).filter(move |i| mask & (1 << i) != 0)
}