#[repr(transparent)]struct SlotH(u32);
Expand description
Entry in the redirection table. Higher Half.
Tuple Fields§
§0: u32
Implementations§
source§impl SlotH
impl SlotH
const DESTINATION_BITS: usize = 8usize
const DESTINATION_OFFSET: usize = 24usize
sourceconst fn with_destination(self, value: u8) -> Self
const fn with_destination(self, value: u8) -> Self
Interrupt destination.
The meaning of destination depends on the destination mode:
For the logical destination mode, destination holds a bit mask made up
of the cores that are candidates for receiving the interrupt.
In the single-core case, this value is 1
, in the multi-core case,
the n
low-order bits needs to be set (with n
being the number of
CPU cores).
Setting the n
low-order bits marks all available cores as candidates
for receiving interrupts and thereby balancing the number of interrupts
between the cores.
Bits: 24..32
sourceconst fn destination(&self) -> u8
const fn destination(&self) -> u8
Interrupt destination.
The meaning of destination depends on the destination mode:
For the logical destination mode, destination holds a bit mask made up
of the cores that are candidates for receiving the interrupt.
In the single-core case, this value is 1
, in the multi-core case,
the n
low-order bits needs to be set (with n
being the number of
CPU cores).
Setting the n
low-order bits marks all available cores as candidates
for receiving interrupts and thereby balancing the number of interrupts
between the cores.
Bits: 24..32
sourcefn set_destination(&mut self, value: u8)
fn set_destination(&mut self, value: u8)
Interrupt destination.
The meaning of destination depends on the destination mode:
For the logical destination mode, destination holds a bit mask made up
of the cores that are candidates for receiving the interrupt.
In the single-core case, this value is 1
, in the multi-core case,
the n
low-order bits needs to be set (with n
being the number of
CPU cores).
Setting the n
low-order bits marks all available cores as candidates
for receiving interrupts and thereby balancing the number of interrupts
between the cores.
Bits: 24..32