Module rstubs::arch::int::lapic

Abstractions for the local APIC for timers, IPI and internal interrupt

Structs

• APICBaseAddr 🔒
  Register for reconfiguring the base address
• DFR 🔒
  Destination Format Register, bits 0-27 RO, bits 28-31 R/W
• EoI 🔒
  EOI Register, WO
• Identification 🔒
  Local APIC ID Register, R/W
• InterruptCmdH 🔒
  Interrupt Command Register 2, R/W
• InterruptCmdL 🔒
  Interrupt Command Register 1, R/W
• LApic
  Abstracts the local APICs (which is integrated into every CPU core)
• LApicVer 🔒
  Local APIC Version Register, RO
• LogicalDst 🔒
  Logical Destination Register, R/W
• SVR 🔒
  Spurious Interrupt Vector Register, bits 0-8 R/W, bits 9-1 R/W
• TPR 🔒
  Task Priority Register, R/W
• TimerCCR 🔒
  LApic timer current counter register, RO
• TimerCtrl 🔒
  LApic timer control register, R/W
• TimerDCR 🔒
  LApic timer divide configuration register, RW
• TimerICR 🔒
  LApic timer initial counter register, R/W

Enums

• DeliveryMode 🔒
  Delivery mode specifies the type of interrupt sent to the CPU.
• IPIDestination
  Destination for an inter-processor interrupt
• TimerMode 🔒
  Timer mode.

Constants

• DFR_MODEL_CLUSTER 🔒
• DFR_MODEL_FLAT 🔒

Statics

• LAPIC
  The LAPIC instance, that is different for each cpu core.

Functions

• lapic_div 🔒
  Converts the divider to the lapic format
• us_to_counter 🔒
  Converts micro seconds to lapic counter configs