Interrupt Command. More...

Public Member Functions
	InterruptCommand ()=default
	Default constructor.

Public Attributes
struct {

Register value_low
	First, low-order register.

Register value_high
	Second, high-order register.

};
	I/O redirection-table entry.

Detailed Description

Interrupt Command.

See also: ISDMv3 10.6.1 Interrupt Command Register (ICR)

Member Data Documentation

◆ [struct]

struct { ... } LAPIC::IPI::InterruptCommand

I/O redirection-table entry.

Every entry in the redirection table represents an external source of interrupts and has a size of 64 bits. Due to the I/O APIC registers being only 32 bits wide, the 64-bit value is split in two 32 bit values.

◆ delivery_mode

enum DeliveryMode LAPIC::IPI::InterruptCommand::delivery_mode

The delivery mode denotes the way the interrupts will be delivered to the local CPU cores, respectively to their local APICs.

For StuBS, we use DeliveryMode::LowestPriority, as all CPU cores have the same priority and we want to distribute interrupts evenly among them. It, however, is not guaranteed that this method of load balancing will work on every system.

◆ delivery_status

enum DeliveryStatus LAPIC::IPI::InterruptCommand::delivery_status

Delivery status holds the current status of interrupt delivery.

Note: This field is read only; write accesses to this field will be ignored.

◆ destination

uint64_t LAPIC::IPI::InterruptCommand::destination

Interrupt destination.

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores, see Core::count() ). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Note: This form of load balancing depends on the hardware's behavior and may not work on all systems in the same fashion. Most notably, in QEMU all interrupts are sent to the BSP (core 0).

◆ destination_mode

enum DestinationMode LAPIC::IPI::InterruptCommand::destination_mode

The destination mode defines how the value stored in destination will be interpreted.

For StuBS, we use DestinationMode::Logical.

◆ level

enum Level LAPIC::IPI::InterruptCommand::level

The polarity denotes when an interrupt should be issued.

For StuBS, we use Polarity::High (i.e., when the interrupt line is, logically, 1).

◆ trigger_mode

enum TriggerMode LAPIC::IPI::InterruptCommand::trigger_mode

The trigger mode states whether the interrupt signaling is level or edge triggered.

StuBS uses TriggerMode::Edge for Keyboard and Timer, the (optional) serial interface, however, needs TriggerMode::Level.

◆ vector

uint64_t LAPIC::IPI::InterruptCommand::vector

Interrupt vector in the Interrupt Descriptor Table (IDT) will be activated when the corresponding external interrupt triggers.

The documentation for this union was generated from the following file:

machine/lapic_ipi.cc

Public Member Functions

Public Attributes