pub enum DatType {
Null = 0,
DataTLB = 1,
InstructionTLB = 2,
UnifiedTLB = 3,
LoadOnly = 4,
StoreOnly = 5,
Unknown = 6,
}
Expand description
Deterministic Address Translation cache type (EDX bits 04 – 00)
Variants§
Null = 0
Null (indicates this sub-leaf is not valid).
DataTLB = 1
InstructionTLB = 2
UnifiedTLB = 3
Some unified TLBs will allow a single TLB entry to satisfy data read/write and instruction fetches. Others will require separate entries (e.g., one loaded on data read/write and another loaded on an instruction fetch) . Please see the Intel® 64 and IA-32 Architectures Optimization Reference Manual for details of a particular product.