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Core Namespace Reference

Implements an abstraction for CPU internals. More...

Namespaces

namespace  Interrupt
 Exception and Interrupt control.
 

Classes

class  CR
 Access to the Control Register. More...
 
class  MSR
 Access to the Model-Specific Register (MSR) More...
 

Enumerations

enum  CR0 {
  CR0_PE = 1 << 0 , CR0_MP = 1 << 1 , CR0_EM = 1 << 2 , CR0_TS = 1 << 3 ,
  CR0_ET = 1 << 4 , CR0_NE = 1 << 15 , CR0_WP = 1 << 16 , CR0_AM = 1 << 18 ,
  CR0_NW = 1 << 29 , CR0_CD = 1 << 30 , CR0_PG = 1 << 31
}
 Control Register 0. More...
 
enum  CR4 {
  CR4_VME = 1 << 0 , CR4_PVI = 1 << 1 , CR4_TSD = 1 << 2 , CR4_DE = 1 << 3 ,
  CR4_PSE = 1 << 4 , CR4_PAE = 1 << 5 , CR4_MCE = 1 << 6 , CR4_PGE = 1 << 7 ,
  CR4_PCE = 1 << 8 , CR4_OSFXSR = 1 << 9 , CR4_OSXMMEXCPT = 1 << 10 , CR4_UMIP = 1 << 11 ,
  CR4_VMXE = 1 << 13 , CR4_SMXE = 1 << 14 , CR4_FSGSBASE = 1 << 16 , CR4_PCIDE = 1 << 17 ,
  CR4_OSXSAVE = 1 << 18 , CR4_SMEP = 1 << 20 , CR4_SMAP = 1 << 21 , CR4_PKE = 1 << 22
}
 Control Register 4. More...
 
enum  MSRs {
  MSR_PLATFORM_INFO = 0xce , MSR_TSC_DEADLINE = 0x6e0 , MSR_SYSENTER_CS = 0x174 , MSR_SYSENTER_ESP = 0x175 ,
  MSR_SYSENTER_EIP = 0x176
}
 Model-Specific Register Identifiers. More...
 
enum  MSR_EFER {
  MSR_EFER_SCE = 1 << 0 , MSR_EFER_LME = 1 << 8 , MSR_EFER_LMA = 1 << 10 , MSR_EFER_NXE = 1 << 11 ,
  MSR_EFER_SVME = 1 << 12 , MSR_EFER_LMSLE = 1 << 13 , MSR_EFER_FFXSR = 1 << 14 , MSR_EFER_TCE = 1 << 15
}
 

Functions

void init ()
 Initialize this CPU core.
 
void exit ()
 Deinitialize this CPU core.
 
unsigned getID ()
 Get the ID of the current CPU core using LAPIC::getID() with an internal lookup table.
 
unsigned count ()
 Get number of available CPU cores.
 
unsigned countOnline ()
 Get number of successfully started (and currently active) CPU cores.
 
bool isOnline (uint8_t core_id)
 Check if CPU core is currently active.
 
void pause ()
 Gives the core a hint that it is executing a spinloop and should sleep "shortly".
 
void idle ()
 Halt the CPU core until the next interrupt.
 
void die ()
 Permanently halts the core.
 

Variables

const unsigned MAX = 8
 Maximum number of supported CPUs.
 

Detailed Description

Implements an abstraction for CPU internals.

These internals include functions to allow or deny interrupts, access control registers.

Enumeration Type Documentation

◆ CR0

enum Core::CR0

Control Register 0.

See also
ISDMv3, 2.5 Control Registers
Enumerator
CR0_PE 

Protected Mode enabled.

CR0_MP 

Monitor co-processor.

CR0_EM 

Emulation (no x87 floating-point unit present)

CR0_TS 

Task switched.

CR0_ET 

Extension type.

CR0_NE 

Numeric error.

CR0_WP 

Write protect.

CR0_AM 

Alignment mask.

CR0_NW 

Not-write through caching.

CR0_CD 

Cache disable.

CR0_PG 

Paging.

◆ CR4

enum Core::CR4

Control Register 4.

See also
ISDMv3, 2.5 Control Registers
Enumerator
CR4_VME 

Virtual 8086 Mode Extensions.

CR4_PVI 

Protected-mode Virtual Interrupts.

CR4_TSD 

Time Stamp Disable.

CR4_DE 

Debugging Extensions.

CR4_PSE 

Page Size Extension.

CR4_PAE 

Physical Address Extension.

CR4_MCE 

Machine Check Exception.

CR4_PGE 

Page Global Enabled.

CR4_PCE 

Performance-Monitoring Counter enable.

CR4_OSFXSR 

Operating system support for FXSAVE and FXRSTOR instructions.

CR4_OSXMMEXCPT 

Operating System Support for Unmasked SIMD Floating-Point Exceptions.

CR4_UMIP 

User-Mode Instruction Prevention.

CR4_VMXE 

Virtual Machine Extensions Enable.

CR4_SMXE 

Safer Mode Extensions Enable.

CR4_FSGSBASE 

Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.

CR4_PCIDE 

PCID Enable.

CR4_OSXSAVE 

XSAVE and Processor Extended States Enable.

CR4_SMEP 

Supervisor Mode Execution Protection Enable.

CR4_SMAP 

Supervisor Mode Access Prevention Enable.

CR4_PKE 

Protection Key Enable.

◆ MSR_EFER

Enumerator
MSR_EFER_SCE 

System Call Extensions.

MSR_EFER_LME 

Long mode enable.

MSR_EFER_LMA 

Long mode active.

MSR_EFER_NXE 

No-Execute Enable.

MSR_EFER_SVME 

Secure Virtual Machine Enable.

MSR_EFER_LMSLE 

Long Mode Segment Limit Enable.

MSR_EFER_FFXSR 

Fast FXSAVE/FXRSTOR instruction.

MSR_EFER_TCE 

Translation Cache Extension.

◆ MSRs

enum Core::MSRs

Model-Specific Register Identifiers.

Selection of useful identifiers.

See also
ISDMv4
Enumerator
MSR_PLATFORM_INFO 

Platform information including bus frequency (Intel)

MSR_TSC_DEADLINE 

Register for LAPIC::Timer Deadline mode.

MSR_SYSENTER_CS 

Contains ring 0 code segment (CS)

MSR_SYSENTER_ESP 

The kernel's ESP for SYSENTER.

MSR_SYSENTER_EIP 

The kernel's EIP for SYSENTER. This is the address of your SYSENTER entry point.

Function Documentation

◆ count()

unsigned Core::count ( )

Get number of available CPU cores.

Returns
total number of cores

◆ countOnline()

unsigned Core::countOnline ( )

Get number of successfully started (and currently active) CPU cores.

Returns
total number of online cores

◆ die()

void Core::die ( )
inline

Permanently halts the core.

Permanently halts the current CPU core. Internally, this function first disables the interrupts via cli and then halts the CPU core using hlt. As halted CPU cores can only be woken by interrupts, it is guaranteed that this core will be halted until the next reboot. The execution of die never returns. On multicore systems, only the executing CPU core will be halted permanently, other cores will continue execution.

See also
ISDMv2, Chapter 3. CLI - Clear Interrupt Flag
ISDMv2, Chapter 3. HLT - Halt

◆ exit()

void Core::exit ( )

Deinitialize this CPU core.

Mark this Core as offline

Note
Should only be called from kernel_init() after returning from main() or main_ap().

◆ getID()

unsigned Core::getID ( )

Get the ID of the current CPU core using LAPIC::getID() with an internal lookup table.

Returns
ID of current Core (a number between 0 and Core::MAX)

◆ idle()

void Core::idle ( )
inline

Halt the CPU core until the next interrupt.

Halts the current CPU core such that it will wake up on the next interrupt. Internally, this function first enables the interrupts via sti and then halts the core using hlt. Halted cores can only be woken by interrupts. The effect of sti is delayed by one instruction, making the sequence sti hlt atomic (if interrupts were disabled previously).

See also
ISDMv2, Chapter 4. STI - Set Interrupt Flag
ISDMv2, Chapter 3. HLT - Halt

◆ init()

void Core::init ( )

Initialize this CPU core.

Mark this core as online and setup the cores LAPIC by assigning it a unique logical APIC ID

Note
Should only be called from kernel_init() during startup.

◆ isOnline()

bool Core::isOnline ( uint8_t core_id)

Check if CPU core is currently active.

Parameters
core_idID of the CPU core
Returns
true if successfully started and is currently active

◆ pause()

void Core::pause ( )
inline

Gives the core a hint that it is executing a spinloop and should sleep "shortly".

Improves the over-all performance when executing a spinloop by waiting a short moment reduce the load on the memory.

See also
ISDMv2, Chapter 4. PAUSE - Spin Loop Hint