Module rstubs::arch::regs

Abstractions for cpu flags and control registers

Structs

• Cr0
  Contains system control flags that control operating mode and states of the processor.
• Cr2
  Contains the page-fault linear address.
• Cr3
  Contains the physical address of the base of the paging-structure hierarchy and two flags (PCD and PWT). Only the most-significant bits (less the lower 12 bits) of the base address are specified; the lower 12 bits of the address are assumed to be 0. The first paging structure must thus be aligned to a page (4-KByte) boundary. The PCD and PWT flags control caching of that paging structure in the processor’s internal data caches (they do not control TLB caching of page-directory information).
• Flags
  The RFLAGS register.