Struct rstubs::arch::regs::Cr3

#[repr(transparent)]
pub struct Cr3(pub u32);

Contains the physical address of the base of the paging-structure hierarchy and two flags (PCD and PWT). Only the most-significant bits (less the lower 12 bits) of the base address are specified; the lower 12 bits of the address are assumed to be 0. The first paging structure must thus be aligned to a page (4-KByte) boundary. The PCD and PWT flags control caching of that paging structure in the processor’s internal data caches (they do not control TLB caching of page-directory information).

When using the physical address extension, the CR3 register contains the base address of the page-directory-pointer table. In IA-32e mode, the CR3 register contains the base address of the PML4 table.

Tuple Fields

0: u32

Implementations

impl Cr3

pub fn read() -> Self

pub unsafe fn write(self)