rstubs::arch::int

Module lapic

Source
Expand description

Abstractions for the local APIC for timers, IPI and internal interrupt

Structs§

  • APICBaseAddr 🔒
    Register for reconfiguring the base address
  • DestFormat 🔒
    Destination Format Register.
  • EndOfInt 🔒
    EOI Register, WO
  • Identification 🔒
    Local APIC ID Register.
  • InterruptCmdH 🔒
    Interrupt Command Register 2, R/W
  • InterruptCmdL 🔒
    Interrupt Command Register 1, R/W
  • LApic
    Abstracts the local APICs (which is integrated into every CPU core)
  • LogicalDst 🔒
    Logical Destination Register.
  • SpuriousInt 🔒
    Spurious Interrupt Vector Register.
  • TaskPrio 🔒
    Task Priority Register, R/W
  • TimerCount 🔒
    LApic timer current counter register, RO
  • TimerCtrl 🔒
    LApic timer control register, R/W
  • TimerDiv 🔒
    LApic timer divide configuration register, RW
  • TimerInitCount 🔒
    LApic timer initial counter register, R/W
  • Version 🔒
    Local APIC Version Register, RO

Enums§

  • DeliveryMode 🔒
    Delivery mode specifies the type of interrupt sent to the CPU.
  • Destination
    Destination for an inter-processor interrupt
  • TimerMode 🔒
    Timer mode.

Constants§

Statics§

  • LAPIC
    The LAPIC instance, that is different for each cpu core.