Struct InterruptCmdH

#[repr(transparent)]
struct InterruptCmdH(u32);

Interrupt Command Register 2, R/W

Tuple Fields

0: u32

Implementations

impl InterruptCmdH

const DESTINATION_BITS: usize = 8usize

const DESTINATION_OFFSET: usize = 24usize

const fn new() -> Self

Creates a new default initialized bitfield.

const fn from_bits(bits: u32) -> Self

Convert from bits.

const fn into_bits(self) -> u32

Convert into bits.

const fn destination(&self) -> u8

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Bits: 24..32

const fn with_destination_checked(self, value: u8) -> Result<Self, ()>

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Bits: 24..32

const fn with_destination(self, value: u8) -> Self

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Bits: 24..32

fn set_destination(&mut self, value: u8)

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Bits: 24..32

fn set_destination_checked(&mut self, value: u8) -> Result<(), ()>

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Bits: 24..32

Trait Implementations

impl Clone for InterruptCmdH

fn clone(&self) -> InterruptCmdH

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for InterruptCmdH

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for InterruptCmdH

fn default() -> Self

Returns the “default value” for a type.

impl From<InterruptCmdH> for u32

fn from(v: InterruptCmdH) -> u32

Converts to this type from the input type.

impl From<u32> for InterruptCmdH

fn from(v: u32) -> Self

Converts to this type from the input type.

impl IOMem for InterruptCmdH

const OFFSET: usize = 784usize

impl Copy for InterruptCmdH