Design and Implementation of a Graphical Simulator for a Pipelined Processor Architecture

The goal of this thesis is to design, implement and evaluate a CPU simulator for a pipelined MIPS-like architecture with a graphical presentation on the block-diagram level. As part of the work you will also explore and characterize different pipeline processor architectures.

In contrast to other simulation approaches, this simulator should be rewindable by single clock steps at any point during simulation. Current and previous values of wires and registers should be inspectable by the user. Furthermore, you will explore the possibility of tracing the origins and flows of values on different wires and units across the pipeline. You should also investigate on the feasibility of optional and user-configurable units. The implementation will be based on an existing prototype that shows some basic features of the desired design, employing state-of-the-art web technologies (HTML, SVG and JavaScript). As part of the work, you will compare the design with other similar simulation approaches and (optionally) with emulators based on hardware description languages.

The implementation is to be evaluated with a set of test cases for specific units and the whole simulator, covering all edge cases. Other interesting evaluation topics are the simulator's performance characteristics and quantitative and qualitative comparisons with other simulation solutions.

Further Reading

David Patterson, John Hennessy. Computer Organization and Design (987-0123744937)