Interaction-Level Specialization of RISC-V Soft Cores for Zephyr RTOS with ARA

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Context

Within the AHA project, we focus on optimizing embedded systems by specialization of the OS itself. Using the Automatic Real-time Analyzer (ARA), we perform static analysis to enable extensive tailoring of real-time operating systems (RTOS) to the application. The operating system is generated specifically for a single application to provide exactly the required functionality. As a result, we improve non-functional system properties like delay or memory footprint, which can reduce hardware costs and energy consumption. Not only the operating system can be specialized; it is also possible to specialize the underlying hardware as well.

Problem

The idea of pushing parts of the operating system into hardware is not new. There is a lot of related work, where parts of the OS like the scheduler are moved completely into hardware blocks next to the CPU. Compared to this approach, we target a much tighter integration, the interactions with specific instances could be moved right into the CPU pipeline. Using ARA, we can analyze those interactions and instances at compile-time, enabling the static specialization of the RTOS and the hardware 1. Instead of high-level message queue operations like k_msgq_put() or k_msgq_get(), a single custom RISC-V instruction could be executed 2. This will result in reduced jitter and optimized kernel path timing. Thus, a better Real-Time behavior is achieved by minimizing the worst-case execution time and improving the predictability.

Goal

The minimal goal of this thesis is to have interaction-specific specialized instructions for the Zephyr RTOS in the Vexriscv Soft Core 3. Using Python, the Vexriscv CPU can be modified to include custom instructions or registers. The Radiona ULX3S board is based on the Lattice ECP5 FPGA and supports single- and multicore VexRiscv-based systems and the required toolchain is Open-Source 4. In order to leverage the new instructions properly, the instance and interaction analysis results in ARA shall be transferred to the generation phase of the SoC.

Topics: Python, FPGA, RISC-V, Hardware, ISA, Real-Time Operating System

References

LCTES Conference A
OSEK-V: Application-Specific RTOS Instantiation in Hardware
Christian Dietrich, Daniel LohmannProceedings of the 2017 ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES '17)ACM Press2017.
PDF Raw Data 10.1145/3078633.3078637 [BibTex]
RTAS Conference A
ARA: Static Initialization of Dynamically-Created System Objects
Björn Fiedler, Gerion Entrup, Christian Dietrich, Daniel LohmannProceedings of the 27th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'21)2021.
PDF Details Video Teaser Video 10.1109/RTAS52030.2021.00039 [BibTex]

Design und Implementierung eines Zephyr-RTOS-Modells für ARA zur statischen Whole-System-Analyse

Extend ARA - a (real-time) operating system (RTOS) analyzer - for analysis of Zephyr, an RTOS guided by the Linux Foundation

 
Typ
Bachelorarbeit

 
Status
abgeschlossen

 
Supervisors
Gerion Entrup
Daniel Lohmann

 
Project
AHA

 
Bearbeiter
Kenny Albes (abgegeben: 28. Feb 2021)