Entry in the redirection table. More...

#include <ioapic_registers.h>

Public Member Functions
	RedirectionTableEntry (Register value_low, Register value_high)
	Constructor for an redirection-table entry.

Public Attributes
uint64_t	vector: 8
	Interrupt vector in the Interrupt Descriptor Table (IDT) will be activated when the corresponding external interrupt triggers.

DeliveryMode	delivery_mode: 3
	The delivery mode denotes the way the interrupts will be delivered to the local CPU cores, respectively to their local APICs.

DestinationMode	destination_mode: 1
	The destination mode defines how the value stored in destination will be interpreted.

DeliveryStatus	delivery_status: 1
	Delivery status holds the current status of interrupt delivery.

Polarity	polarity: 1
	The polarity denotes when an interrupt should be issued.

uint64_t	remote_irr: 1
	The remote IRR bit indicates whether the local APIC(s) accept the level interrupt.

TriggerMode	trigger_mode: 1
	The trigger mode states whether the interrupt signaling is level or edge triggered.

InterruptMask	interrupt_mask: 1
	Mask or unmask interrupts for a particular, external source.

uint64_t	: 39
	Reserved, do not modify.

uint64_t	destination: 8
	Interrupt destination.

Register	value_low
	Low-order 32 bits (for the register with the smaller index)

Register	value_high
	High-order 32 bits (for the register with the higher index)

Detailed Description

Entry in the redirection table.

The redirection table begins with I/O APIC register 0x10 and ends at 0x3f.

Each entry has a size of 64 bit, equaling two I/O APIC registers. For instance, entry 0 is stored in registers 0x10 and 0x11, in which the low-order 32 bit (equals value_low) and high-order 32 bit (equals value_high) need to be stored.

The union defined below provides an overlay allowing convenient modification of individual bits, while the 32-bit values value_low and value_high can be used for writing to the I/O APIC registers.

Note: Type punning is indeed undefined behavior in C++. However, gcc explicitly allows this construct as a language extension. Some compilers (other than gcc might allow this feature only by disabling strict aliasing (-fno-strict-aliasing). In StuBS we use this feature extensively due to the improved code readability.

See also: IO-APIC manual, page 11-13

Constructor & Destructor Documentation

◆ RedirectionTableEntry()

IOAPIC::RedirectionTableEntry::RedirectionTableEntry	(	Register	value_low,
		Register	value_high )

inline

Constructor for an redirection-table entry.

Every entry in the redirection table represents an external source of interrupts and has a size of 64 bits. Due to the I/O APIC registers being only 32 bits wide, the constructor takes two 32 bit values.

Parameters

value_low	First, low-order 32 bit value
value_high	Second, high-order 32 bit value

Member Data Documentation

◆ delivery_mode

DeliveryMode IOAPIC::RedirectionTableEntry::delivery_mode

The delivery mode denotes the way the interrupts will be delivered to the local CPU cores, respectively to their local APICs.

For StuBS, we use LOWEST_PRIORITY, as all CPU cores have the same priority and we want to distribute interrupts evenly among them. It, however, is not guaranteed that this method of load balancing will work on every system.

◆ delivery_status

DeliveryStatus IOAPIC::RedirectionTableEntry::delivery_status

Delivery status holds the current status of interrupt delivery.

Note: This field is read only; write accesses to this field will be ignored.

◆ destination

uint64_t IOAPIC::RedirectionTableEntry::destination

Interrupt destination.

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores, see Core::count() ). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Note: This form of load balancing depends on the hardware's behavior and may not work on all systems in the same fashion. Most notably, in QEMU all interrupts are sent to the BSP (core 0).

◆ destination_mode

DestinationMode IOAPIC::RedirectionTableEntry::destination_mode

The destination mode defines how the value stored in destination will be interpreted.

For StuBS, we use LOGICAL

◆ interrupt_mask

InterruptMask IOAPIC::RedirectionTableEntry::interrupt_mask

Mask or unmask interrupts for a particular, external source.

The interrupt mask denotes whether interrupts should be accepted/unmasked (value UNMASKED) or ignored/masked (value MASKED).

◆ polarity

Polarity IOAPIC::RedirectionTableEntry::polarity

The polarity denotes when an interrupt should be issued.

For StuBS, we usually use HIGH (i.e., when the interrupt line is, logically, 1).

◆ remote_irr

uint64_t IOAPIC::RedirectionTableEntry::remote_irr

The remote IRR bit indicates whether the local APIC(s) accept the level interrupt.

Once the LAPIC sends an End Of Interrupt (EOI), this bit is reset to 0.

Note: This field is read only and is only meaningful for level-triggered interrupts.

◆ trigger_mode

TriggerMode IOAPIC::RedirectionTableEntry::trigger_mode

The trigger mode states whether the interrupt signaling is level or edge triggered.

StuBS uses EDGE for the Timer, the Keybaord and (optional) serial interface need LEVEL

The documentation for this union was generated from the following file:

machine/ioapic_registers.h

Public Member Functions

Public Attributes