Development and Analysis of an AUTOSAR Real-Time Operating System on a Multicore RISC-V Hardware Platform

• Typ der Arbeit: Bachelorarbeit
• Status der Arbeit: reserviert
• Projekte: AHA
• Betreuer: Andreas Kässens, Daniel Lohmann

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Context

Within the AHA project, we focus on optimizing embedded systems by specialization of the OS itself. Using the Automatic Real-time Analyzer (ARA), we perform static analysis to enable extensive tailoring of real-time operating systems (RTOS) to the application. The operating system is generated specifically for a single application to provide exactly the required functionality. As a result, we improve non-functional system properties like delay or memory footprint, which can reduce hardware costs and energy consumption.

Problem

Currently, ARA can generate RISC-V compatible system images that are executed in QEMU. To quantify the performance benefits caused by our system tailoring in ARA ¹, the application shall be executed on real multicore RISC-V hardware. In order to achieve this, the student has to understand and modify the compilation toolchain, build steps, memory layout, system startup sequence etc. to build the system for a real board. While the QEMU virtual machine is forgiving bugs, the hardware platform can have specific pitfalls, which might need some debugging and reading the RISC-V specification ².

Goal

The minimal goal of this thesis is to have multicore AUTOSAR-compatible test applications running on a RISC-V board such as the BeagleV®-Fire Single-Board-Computer ³. Further, the RISC-V system libraries shall be extended with timing measurement support by making use of the RISC-V performance counters like mcycle ². As an optional extension, user/kernel isolation could be added to the implementation.

To evaluate the RTOS, it shall be compared to available measurements from an ARM-based platform (Raspberry Pi 4). A fully implemented system should support the following:

• automatically programming/booting the board with the new RTOS (e.g. using TFTP)
• executing test cases and verifying their success
• timing measurements of code sections using RISC-V performance counters
• comparison and analysis of tailored system variants
• comparison with the implementation for ARM, specifically the Raspberry Pi 4

Topics: C++, C, RISC-V, Hardware, Real-Time Operating System

References

RTSJ Journal
Applied static analysis and specialization of cross-core syscalls for multi-core AUTOSAR OS

Gerion Entrup, Andreas Kässens, Björn Fiedler, Daniel LohmannReal-Time SystemsSpringer2024.
PDF 10.1007/s11241-024-09429-1 [BibTex]

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BibTex Entry

@article{entrup:24:rts,
author = {Gerion Entrup and Andreas Kässens and Björn Fiedler and Daniel Lohmann},
doi = {10.1007/s11241-024-09429-1},
entrysubtype = {Journal},
journaltitle = {Real-Time Systems},
month = {October},
publisher = {Springer},
title = {Applied static analysis and specialization of cross-core syscalls for multi-core {AUTOSAR OS}},
year = {2024},
}

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Implementation of Optimized AUTOSAR Systems for RISC-V with ARA

Extending the AUTOSAR Synthesis in ARA to support multicore RISC-V targets

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Typ

Bachelorarbeit

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Status

abgeschlossen

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Supervisors

Andreas Kässens
Daniel Lohmann

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Project

AHA

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Bearbeiter

Arved Blöcker (abgegeben: 05. Aug 2024)

Synthesis of Optimized AUTOSAR Embedded Systems: Automated System-Call Specialization and Lock Elision on Multicore Applications as a Whole-System Approach

Implement and evaluate an AUTOSAR synthesis with Lock Elision [PDF]

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Typ

Masterarbeit

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Status

abgeschlossen

---

 

Supervisors

Gerion Entrup
Daniel Lohmann

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Project

AHA

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Bearbeiter

Andreas Kässens (abgegeben: 14. Jun 2023)