Systems Research and Architecture System und Rechnerarchitektur SRA
a SRA Theses On the Power Estimation of a RISC-V Platform using Performance Monitoring Counters and RTOS Events

On the Power Estimation of a RISC-V Platform using Performance Monitoring Counters and RTOS Events

In this thesis we want to profile the power consumption of an existing RISC-V SoC, and create a model with which we can estimate power consumption during the runtime. In the past, this was primarily done using performance monitoring counters(PMCs)[1].

The main task is to create an evaluation setup, which collects those counters and power measurements during representative workloads, a promising target is the BEEBS benchmarksuite[2]. For this we provide the SoC[3] and measurement devices [4,5]. Based on those measurements a model can be trained, which allows an estimation of the power consumption during the operative phase of the system[1].

As a next step, we can extend the setup to use hooks provided by an operating system, e.g. the tracing subsystem of Zephyr[6]. OS events can be used instead of hardware PMCs, like the amount of context switches, access to operating resources like queues, etc. as model parameters.

[1] A Study on the Use of Performance Counters to Estimate Power in Microprocessors

[2] https://github.com/mageec/beebs

[3] ESP32-C3 board

[4] Rigol DM3058/E

[5] python-usbtmc

[6] https://docs.zephyrproject.org/latest/services/tracing/index.html