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//! Serial Console
#![allow(unused)]

use core::fmt;

use bitfield_struct::bitfield;

use crate::arch::io::{Port, PortValue};

/// Serial port 1 base address
pub const COM1: u16 = 0x3F8;

/// Serial console
pub struct Serial {
    /// Base address of the data port
    base: u16,
}

impl Serial {
    pub const fn new(base: u16) -> Self {
        Self { base }
    }

    /// Initialize the serial output with:
    /// - baud rate of 115200
    /// - 8 bit word length
    /// - 1 stop bit
    /// - no parity
    pub fn init(&mut self) {
        unsafe {
            // Disable interrupts
            self.int_en().write(0);

            // Enable DLAB -> data and int_en now set the baud rate
            self.line_ctl()
                .write(LineCtl::new().with_divisor_latch_access(true));

            todo!("BSB A1 - Set baud rate, word length, stop bits, and parity (also disable divisor_latch_access)");

            // Enable and clear FIFO
            self.fifo_ctl().write(
                FifoCtl::new()
                    .with_enable(true)
                    .with_clear_receive(true)
                    .with_clear_transmit(true),
            );

            // Modem Control: OUT2 (0000 1011) must be set for interrupt
            self.modem_ctl().write(
                ModemCtl::new()
                    .with_data_terminal_ready(true)
                    .with_request_to_send(true)
                    .with_out2(true),
            );
        }
    }

    /// Write a single byte to the output channel
    fn send_byte(&mut self, b: u8) {
        // Wait for the serial port's fifo to be empty
        // TODO: BSB A1
    }

    /// Data register (or lower half of the divisor if `divisor_latch_access` is enabled)
    const fn data(&self) -> Port<u8> {
        Port::new(self.base)
    }
    /// Interrupt enable register (or upper half of the divisor if `divisor_latch_access` is enabled)
    const fn int_en(&self) -> Port<u8> {
        Port::new(self.base + 1)
    }
    const fn fifo_ctl(&self) -> Port<FifoCtl> {
        Port::new(self.base + 2)
    }
    const fn line_ctl(&self) -> Port<LineCtl> {
        Port::new(self.base + 3)
    }
    const fn modem_ctl(&self) -> Port<ModemCtl> {
        Port::new(self.base + 4)
    }
    const fn line_status(&self) -> Port<LineStatus> {
        Port::new(self.base + 5)
    }
}

impl fmt::Write for Serial {
    fn write_str(&mut self, s: &str) -> fmt::Result {
        for b in s.bytes() {
            self.send_byte(b);
        }
        Ok(())
    }
}

/// FIFO Control Register
#[bitfield(u8)]
struct FifoCtl {
    /// 0 means disabled ^= conforming to 8250a
    enable: bool,
    /// Clear the receive buffer
    clear_receive: bool,
    /// Clear the transmit buffer
    clear_transmit: bool,
    dma_mode_select: bool,
    #[bits(2)]
    __: (),
    trigger_receive: bool,
    __: bool,
}
impl PortValue for FifoCtl {
    type I = u8;
}

/// Line Control Register
#[bitfield(u8)]
struct LineCtl {
    /// bits per character | 5 | 6 | 7 | 8
    /// -------------------|---|---|---|---
    /// word length value  | 0 | 1 | 2 | 3
    #[bits(2)]
    word_length: u8,
    /// false = one stop bit, true = 1.5/2 stop bits
    stop_bits: bool,
    /// If enabled, add a parity bit
    parity: bool,
    even_parity: bool,
    stick_parity: bool,
    set_break: bool,
    /// If enabled, the [Serial::data] and [Serial::int_en] registers
    /// set the divisor (baud rate) instead of their normal function
    divisor_latch_access: bool,
}
impl PortValue for LineCtl {
    type I = u8;
}

/// Modem Control Register
#[bitfield(u8)]
struct ModemCtl {
    data_terminal_ready: bool,
    request_to_send: bool,
    out1: bool,
    /// must be set for interrupts!
    out2: bool,
    do_loop: bool,
    #[bits(3)]
    __: (),
}
impl PortValue for ModemCtl {
    type I = u8;
}

/// Line Status Register
#[bitfield(u8)]
struct LineStatus {
    /// Set when there is a value in the receive buffer
    data_ready: bool,
    overrun_error: bool,
    parity_error: bool,
    framing_error: bool,
    break_interrupt: bool,
    transmitter_holding_register: bool,
    /// Send buffer empty (ready to send)
    transmitter_empty: bool,
    __: bool,
}
impl PortValue for LineStatus {
    type I = u8;
}